The ARM v3 core control module

Introduction - - This module provides core control for v3 architecture ARM processors (lives in Core/ARM/3). The two main configurable options in an ARM v3 core is that of working in big endian and that of working in 26 bit ARM v2 architecture compatibility mode.
Callability
Assembler:  INCLUDE "ARMCoreH.s"
C:  #include "ARMCore.h"
HALError
Module name:  "ARMCore", 0 (0x434d5241, 0x0065726f)
Codes:
0:  (0x00):  Not compatible with local architecture
Portability API not portable
Code not portable
Constituents Entirely written in ARM assembler for speed
Porting notes None
Other Notes You must already be in a supervisor mode to call any part of the module
General use All calls to and from the ARM v3 core control module are prefixed by ARMCore_. The module uses only zero page memory and hence may be called at times when main memory is not functional.

To initialise and finalise the operation of this module, the usual calls ARMCore_Initialise and ARMCore_Finalise are provided. The general purpose call ARMCore_Set is used to set the operation of the core, and the calls ARMCore_Enable32 and ARMCore_Enable26 are provided for specific aspect control. Calls relating to endian control are not provided as they are never practically used - use ARMCore_Set directly if you need to achieve this.

These calls may only be made from a supervisor mode. Interrupts may be undefined.

 

ARMCore_Initialise

Purpose - - Initialises the ARM v3 core control module for subsequent use
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call examines the local ARM core and configures itself to use it. On this version of the module, an error is returned if the core is not v3 architecture.
Notes You must be in a supervisor mode when calling this

 

ARMCore_Finalise

Purpose     Deinitialises the ARM v3 core control module
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use None
Notes You must be in a supervisor mode when calling this

 

ARMCore_Set

Purpose     Sets the future operation of the core
Entry R0 = bits to set
R1 = bits to clear
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call offers the lowest level control of the operation of the core. There are three bits you may specify in R0 or R1, that being:
  • bit 5: enable 32 bit program space (ARMCACHE_SETP32)
  • bit 6: enable 32 bit data space (ARMCACHE_SETD32)
  • bit 7: use big endian words (ARMCACHE_SETBIGENDIAN)

Setting bits takes precedence over clearing bits. Please refer to the ARM ARM (the ARM Architecture Reference Manual) for more information about these bits.
Notes You must be in a supervisor mode when calling this

 

ARMCore_Enable32

Purpose     Enables 32 bit operation
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call internally calls ARMCache_Set with bits 5 & 6 set in R0
Notes You must be in a supervisor mode when calling this

 

ARMCore_Enable26

Purpose     Enables 26 bit operation
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call internally calls ARMCache_Set with bits 5 & 6 set in R1
Notes You must be in a supervisor mode when calling this