The ARM v3 cache control module

Introduction - - This module provides cache control for v3 architecture ARM processors (lives in Core/ARM/3). The cache on this version of the architecture is always unified (ie; both instructions and data are cached there) and processors which use this cache architecture include the Arm6 and Arm7. There is one available operation, that being to entirely flush the unified cache.
Callability
Assembler:  INCLUDE "ARMCacheH.s"
C:  #include "ARMCache.h"
HALError
Module name:  "ARMCache" (0x434d5241, 0x65686361)
Codes:
0:  (0x00):  Reserved
Portability API not portable
Code not portable
Constituents Entirely written in ARM assembler for speed
Porting notes None
Other Notes You must be in a supervisor mode to call any part of the module
General use All calls to and from the ARM v3 cache control module are prefixed by ARMCache_. The module uses only zero page memory and hence may be called at times when main memory is not functional.

To initialise and finalise the operation of this module, the usual calls ARMCache_Initialise and ARMCache_Finalise are provided. The general purpose call ARMCache_Set is used to set the operation of the cache, and the calls ARMCache_EnableUCache, ARMCache_DisableUCache and ARMCache_FlushUCache are provided for specific aspect control.

These calls may only be made from supervisor mode. Interrupts may be undefined.

 

ARMCache_Initialise

Purpose - - Initialises the ARM v3 cache control module for subsequent use
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use None
Notes You must be in a supervisor mode when calling this

 

ARMCache_Finalise

Purpose     Deinitialises the ARM v3 cache control module
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use None
Notes You must be in a supervisor mode when calling this

 

ARMCache_Set

Purpose     Sets the future operation of the cache
Entry R0 = bits to set
R1 = bits to clear
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call offers the lowest level control of the operation of the cache. There is only one bit you may specify in R0 or R1, that being:
  • bit 2: enable unified cache (ARMCACHE_SETUCACHE)

Setting bits takes precedence over clearing bits
Notes You must be in a supervisor mode when calling this

 

ARMCache_EnableUCache

Purpose     Enables the cache
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call internally calls ARMCache_Set with bit 2 (ARMCACHE_SETUCACHE) set in R0
Notes You must be in a supervisor mode when calling this

 

ARMCache_DisableUCache

Purpose     Disables the cache
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is disabled
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Alters zero page memory only
Use This call internally calls ARMCache_Set with bit 2 (ARMCACHE_SETUCACHE) set in R1
Notes You must be in a supervisor mode when calling this

 

ARMCache_FlushUCache

Purpose     Flushes the cache
Entry None
Exit R0 = Null if no error occurred, pointer to HALError otherwise
Interrupts IRQ is unchanged
FIQ is unchanged
Processor Mode Unchanged (see Notes)
Staticity Fully static
Use This call instructs the ARM to mark all the entries in its unified cache as empty
Notes You must be in a supervisor mode when calling this